Field of the Invention
The present invention relates to a pattern generation method.
Description of the Related Art
An exposure apparatus is used in an exposure process of a manufacturing process of a semiconductor device. The exposure apparatus uses light from a light source to illuminate a mask (reticle) on which a circuit pattern of the semiconductor device using an illumination optical system is formed and transfers a pattern of mask onto a wafer using a projection optical system.
Recently, the miniaturization of patterns of the semiconductor devices has been further progressed, and in the exposure process, a Resolution Enhanced Technology such as an off-axis illumination of the illumination optical system or optical proximity correction (OPC) of a pattern of a mask has been used.
A pattern of an entire surface of the mask includes one or a plurality of patterns corresponding to an area of one semiconductor chip. A pattern of one semiconductor chip area is configured by combining circuit pattern groups including a block cell in which functional blocks are formed in one group, an IO unit indicating input/output of data, and a standard cell in the unit of logic element.
When the OPC is performed on the pattern of the mask of the entire semiconductor chip, the amount of correction data of the pattern is huge, which requires several days as a processing time. Therefore, a technique for performing the OPC on the standard cell (hereinafter, referred to as cell OPC) as a previous step of the OPC which is performed on the entire mask pattern has been studied.
As an example in which the OPC is applied to the standard cell, a technique for repeating operations of extracting one cell, applying the OPC to the cell, and registering the completed cell in a library for every cell is discussed (see Japanese Patent No. 3073156).
Further, it is discussed that the mask pattern is classified into a pattern to which the cell OPC is applied and a pattern in which the OPC (hereinafter, referred to as a chip level OPC) is applied to a pattern of the entire surface of the semiconductor chip (see Japanese Patent No. 3827659). Japanese Patent No. 3827659 discusses that the OPC is performed on a pattern for a cell OPC and the cell on which the OPC is performed is registered in a cell library. In addition, Japanese Patent No. 3827659 further discusses a technique for performing the OPC on a chip level OPC applied pattern to generate a mask pattern, after generating a pattern of the semiconductor chip by arranging cells selected from the cell library.
In the meantime, in order to deal with the miniaturization of the pattern, it has become difficult to satisfactorily transfer a desired pattern onto a wafer in a conventional two dimensional layout (extending in horizontal and vertical directions) pattern. Therefore, there is an action which uses an improved technique for a design called as design for manufacturability (DfM) which allows easy processing in a manufacturing process to prevent a hot spot which is detected in a subsequent process from occurring.
A method for producing a pattern in which a pitch restriction is added to the designed pattern which is called a one dimension gridded design rule (1D-GDR) (one dimensional layout) technique is studied for a logic device (see “Low k1 Logic Design using Gridded Design Rules” by Michael C. Smayling et. al, Proc. of SPIE Vol. 6925 (2008)). In the 1D-GDR technique, a line and space (L/S) pattern with a single pitch is formed on a wafer in advance and then a plurality of pattern elements such as a hole pattern or a cut pattern is exposed on an equi-grid with the same size of image in a plurality of locations. With this method, the L/S pattern with a single pitch is cut by the pattern element or the space is filled to produce a device. The 1D-GDR technique may not only have a large exposure margin, but also reduce an area of a cell, as compared with a pattern having a high degree of freedom such as a two dimensional layout pattern which is used in the related art.
Further, as a verification example of the 1D-GDR, a device below 20 nm Node can be formed (see “Sub-20 nm Logic Lithography Optimization with Simple OPC and Multiple Pitch Division” by Michael C. Smayling et. al Proc. Of SPIE Vol. 8327 (2012)).
In the inventions discussed in Japanese Patent Nos. 3073156 and 3827659, the calculation is performed without adjusting an exposure condition of the exposure apparatus when the OPC is performed on the cell. If the cell OPC is performed while fixing the exposure condition, when the exposure condition is not appropriate, a desired image performance cannot be obtained. In that case, if the mask pattern is corrected while adjusting the exposure condition to obtain an appropriate exposure condition when a cell on which the cell OPC is performed is arranged to design the mask pattern to perform the chip level OPC, a line width of the pattern or an amount of correction in a position or a portion to be corrected is increased so that an amount of calculation is increased. Therefore, there is a problem in that a calculating time is increased.
Further, as discussed in Japanese Patent No. 3073156, if the cell OPC is repeatedly applied to every cell, a calculating time for all cells is increased.
Further, a pattern of a cell may be designed to be a cut pattern which is used for one dimensional layout discussed in “Low k1 Logic Design using Gridded Design Rules” by Michael C. Smayling et. al., Proc. of SPIE Vol. 6925 (2008) and “Sub-20 nm Logic Lithography Optimization with Simple OPC and Multiple Pitch Division” by Michael C. Smayling et. al., Proc. Of SPIE Vol. 8327 (2012). However, when the cell OPC discussed in Japanese Patent Nos. 3073156 and 3827659 is performed on the above pattern, the same problem may occur.